Harshal Kothari

System on Chip (SoC) Design Verification Senior Staff Engineer/Manager at Samsung Semiconductor

System on Chip (SoC) Design Verification Senior Staff Engineer/Manager with 9+ years experience working on wide range of custom ASICs on advanced technology nodes: AI/ML Accelerators, HPC 3DIC, Data Center chiplet based 2.5DIC, Automotive, ADAS/FSD, Humanoid Robotics, Application Processors, Mobile Co-processors and XR (AR/VR/MR) SoCs at Foundry Design Services (Hardware) division at Samsung Semiconductor. Leading a team of 6 engineers and helped design and verification of 20+ cutting edge SOC/ASICs Expertise in below domains over complete cycle of Pre-Silicon SoC Design Verification- specification and architecture to RTL simulation, emulation, Power Aware RTL with UPF, Unit Delay and Timing (SDF) Gate Level Simulations (GLS) and Post PnR PGnet Power Aware GLS: - SoC boot and Always-On blocks - High speed die-to-die UCIeStorage (UFS, Unipro, MPHY) - PCIe - CXL - UALINK - HBM - LPDDR/DRAM - Low power management - ARM/RISC-V based CPUs and MCUs - Camera Pipeline with MIPI CSI, DPHY - System control and peripheral IPs - In-system functional safety (MBIST/LBIST via POST/IST) - AMBA bus protocols - Security Proficient in SystemVerilog (SV), Universal Verification Methodology (UVM), Ver…

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